1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with vertical channel transistors and a method for fabricating the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, in a memory device such as a DRAM, a memory cell includes a cell transistor such as a MOSFET. In general, in a MOSFET, source and drain regions are formed in a semiconductor substrate, and a planar channel is formed between the source region and the drain region. Such a MOSFET is generally referred to as a ‘planar channel transistor’.
As the degree of integration and performance continue to improve, a MOSFET fabrication technology has reached a physical limit. For instance, as the size of a memory cell decreases, the size of a MOSFET decreases, and accordingly, the channel length of the MOSFET also decreased. If the channel length of a MOSFET decreases, the characteristics of a memory device are likely to deteriorate as various concerns caused in that data retention characteristics deteriorate.
In consideration of these problems, a vertical channel transistor has been suggested. The vertical channel transistor (VCT) includes a pillar to serve as a vertical channel. A source region and a drain region are formed in top and bottom portions of the pillar. The pillar serves as a channel, and a vertical gate electrode is formed on a sidewall of the pillar. The source region and the drain region are connected with a bit line.
FIG. 1 is a cross-sectional view illustrating a conventional buried bit lines.
Referring to FIG. 1, a plurality of semiconductor body lines 14 are formed on a semiconductor substrate 11 to be separated by trenches 13. The semiconductor body lines 14 are formed through etching using a hard mask layer 12. A passivation layer 15 is formed on the sidewalls of the semiconductor body lines 14 and the surfaces of the trenches 13. Open parts 17 are formed in the passivation layer 15. The open parts 17 open any one sidewall of the semiconductor body lines 14. Buried bit lines 16 partially fill the trenches 13. The buried bit lines 16 connect with the semiconductor body lines 14 through the open parts 17. Each buried bit line 16 connects with any one of two adjacent semiconductor body lines 14. While not shown, upper portions of the semiconductor body lines 14 are etched, and semiconductor pillars, which serve as channels of vertical channel transistors, are formed.
As shown in FIG. 1, in order to connect each buried bit line 16 to the sidewall of any one of two adjacent semiconductor body lines 14, an OSC (one-side-contact) process is applied. In order to accomplish the OSC process, various methods such as a liner layer and tilt ion implantation process, an OSC mask process, and the like have been proposed.
However, these methods fail to form a uniform and reproducible OSC structure due to difficulties in processing. Also, as high integration further proceeds, a concern is caused in that the distance between adjacent buried bit lines 16 becomes narrow and parasitic capacitance (CB) between adjacent buried bit, lines 16 increases. Since the buried bit lines 16 are brought into contact with the semiconductor body lines 14, the parasitic capacitance (CB) between buried bit lines 16 is substantially the capacitance between the semiconductor body line 14 and the buried bit line 16. Accordingly, because the distance between adjacent buried bit lines 16 becomes narrow, the parasitic capacitance (CB) may increase dramatically.
If the parasitic capacitance (CB) between buried bit lines increases in this way, the operation of a device may become inoperable.
Furthermore, in the conventional art, in consideration of the height of semiconductor pillars to serve as channels, high aspect ratio etching is required as an etching process for forming the semiconductor body lines 14. Therefore, since the trenches 13 are formed to have depth of H to include the height of the semiconductor pillars, a concern is raised in that the semiconductor body lines 14 are likely to lean.